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Superlattice Analog-To-Digital Converter

IP.com Disclosure Number: IPCOM000058030D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Van Zeghbroeck, B [+details]

Abstract

A new type of low-temperature analog-to-digital (A/D) converter is proposed which consists of a sample-and-hold input stage followed by a superlattice device with periodic negative conductance, a differentiation circuit and a digital counter. When applying an analog signal, the periodic negative conductance is reproduced as a pulse train in time, each pulse marking a voltage transition, i.e., counting the pulses provides the digitized voltage. The A/D converter arrangement is schematically presented in Fig. l. The analog signal Vin* to be converted is applied to a sample-andhold input stage (S/H) which, in turn, connects to the multi-quantum- well superlattice with the periodic negative conductance. Such a device has, e.g., been described by K.K.