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IMPROVED SIGNAL and DENSITY DYNAMIC RANDOM-ACCESS MEMORY

IP.com Disclosure Number: IPCOM000058039D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Scheuerlein, RE [+details]

Abstract

A dynamic random-access memory (DRAM) cell structure is reported which produces approximately a six-fold increase in signal output by differentially sensing two co-axial cells with three capacitors in a single trench. Alternatively, the two co-axial cells can be organized in a single trench so as to double the density of a DRAM array with each cell being independent of the other. (Image Omitted) In a conventional one device cell structure, as shown in Fig. 1, the cell consists of a capacitive storage element Cs and a transistor T1 utilized as a switch. The device is controlled by a word line WL and bit line BL. The charge Q supplied by a capacitor Cs is proportional to the change in potential difference WV across the plates, i.e., Q = CsWV.