Browse Prior Art Database

Complementary Referencing for Dynamic Array Sensing

IP.com Disclosure Number: IPCOM000058041D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
O'Neil, EF [+details]

Abstract

A complementary transistor is used for a reference cell of a complementary metal oxide silicon (CMOS) dynamic random-access memory array (DRAM) during sensing. A circuit configuration and method for complementary referencing is described which results in fast gate transfer of charge in an overdriven reference cell, thus yielding greater voltage difference between bit lines during sensing without exceeding breakdown voltage limits of device insulators. Referring to the figure, data is stored in a one device cell, e.g., the storage cell comprised of transfer device T2 and its capacitor connected to the substrate. The stored data signal is put on bit line BL when transfer device T2 in a p-type array is selected. Transistor T2 is selected from a positive going pre-charge to ground. The pre-charge potential is Vdd = 3.0 volts.