Storage Sentry Circuit
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15
A technique is described whereby a storage sentry circuit is implemented in computer systems so as to provide monitorization of soft memory errors, so as not to impede system throughput. The circuit also has the ability to correct errors as required. Through this monitorization, the circuit computes the rate of soft errors which are occurring and, if the rate exceeds a certain predetermined value, will post a system interrupt. Under special conditions, the circuit will detect a faulty address line and flag it as an error. The circuit has the ability to detect a soft error and will correct the error and write the corrected data back to the proper location in memory. If a detected error is uncorrectable, the circuit will notify the system that a potential problem exists.