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Pipelined Emulation Assist Processor Sequence Control

IP.com Disclosure Number: IPCOM000058050D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Hannon, ES Kalla, RN [+details]

Abstract

An emulation assist processor (EAP), which emulates System/370 (S/370) instruction, uses two cycles to perform every micro-instruction. The first cycle forms the micro-instruction by ORing the S/370 fields into a skeleton instruction. Then, in the second cycle, the processor executes the instruction and returns status to EAP. A sequence controller for a pipelined EAP, as described in the following, will allow the EAP to form the next micro-instruction while the instruction processing unit (IPU) is executing the current one, and still retain precise interrupt control. This will double the performance of the EAP. To control the EAP, maintain a high degree of pipelining, and minimize wait states, two sequencers are used.