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Sense Amplifier With Split Set Node Disclosure Number: IPCOM000058055D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

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Ohsaki, K Ueda, M [+details]


This is a new sense amplifier for one-device (FET with capacitor storage) dynamic random-access memories, which has two independently controllable set nodes to enable writing of "all 1's" or "all 0's" in a selected row of memory cells at a time. The sense amplifier can be used to rapidly set predetermined data patterns in the memory at the time of memory testing, initialization, clear or the like. The figure shows the present sense amplifier incorporated in a folded bit line one-device memory. The difference from conventional sense amplifiers is the addition of FETs T5, T6 and T7 which provide two independently controllable set nodes N1 and N2.