Engineering Change Pad Sharing With Fusible Links
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15
A method is described that reduces the number of Engineering Change (EC) pads on the top surface of a module substrate with minimal circuitry on the chip and no stage delays to the normal signal paths. The reduction of EC pads allows more area for larger chips. EC pads are reduced by sharing among I/O (Input/Output) terminals, rather than using dedicated EC pads for chip I/O. Fig. 1A and 1B show two I/Os sharing an EC pad. The EC pad is used only when the chip requires an EC affecting one of the two I/Os. Otherwise, if used, the chip I/O is connected directly to an internal wiring layer. The connection to an EC pad is made via a fusible link that is a permanent physical change to the chip or substrate. When the two I/Os are used as inputs, as in Fig.