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Integer Conversion Algorithms for IEEE Binary Floating Point Arithmetic

IP.com Disclosure Number: IPCOM000058084D
Original Publication Date: 1988-Aug-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Goldberg, WD Keung, T Olsson, B Rodriguez, JR Suarez, GA [+details]

Abstract

This article describes a method for performing conversions in a processor from floating point (FP) representation to integer format and from integer format to FP format while adhering to an architecture based on the IEEE binary FP standard. In a floating point unit (FPU) implementation and IEEE binary floating point standard 754-1985, five data formats are defined. The formats include three FP formats; single (32 bits), double (64 bits), and double extended (79 bits). In addition, two integer formats are also supported: short integer (32 bits) and long integer (64 bits). The architecture defines conversions between the integer formats and the double extended FP format.