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Programmable Logic Delay Line and Pulse Generator Enhancement

IP.com Disclosure Number: IPCOM000058122D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Dong, E Groh, W [+details]

Abstract

A technique is described whereby existing programmable delay line and programmable pulse generator modules are enhanced by incorporating switch selection of logical high and logical low for each internal programmable pin of the device. The concept is an improvement over current design which required wire jumpers and provides a more effective and efficient use of the device and reduces testing time. In the development of electronic circuitry, which utilize programmable delay line and programmable pulse generator modules, connections are often required from the programming pins to voltages representing logical low or logical high, in order to select one of the delays or pulses available from the device. These connections were often made by way of mechanical wire jumpers, wire wrapping or external remote switches.