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New Method of Parameterizing Primitive Symbols for Integrated Circuit Layouts

IP.com Disclosure Number: IPCOM000058135D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Lee, JF [+details]

Abstract

A technique is described whereby a new parameterization method permits generic definition of primitive symbols, such as transistors and contacts, in integrated circuit layouts. The method is particularly useful in mapping a stick diagram into mask shapes. It has been applied to compactor layouts, where sidewall transistors and butted contacts are used. Symbolic layouts and compaction of integrated circuits have typically been adapted for layout activity because one symbol can be used to represent objects of different technologies. For example, the same symbol of a pull-up transistor can be used to represent a load transistor in NMOS technology, or it can represent a P-type transistor in CMOS technology.