Browse Prior Art Database

Automatic Vertical Hold Circuit

IP.com Disclosure Number: IPCOM000058141D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Morrish, AJ [+details]

Abstract

Video displays with multiple vertical format mode often need additional circuitry to vary the free-running frequency in order that the oscillator can always lock at every frequency displayed. An additional requirement is to prevent excessive overscanning during free running by appropriate control. The circuit described in the figure simplifies this requirement. A CMOS input TTL compatible logic XNOR gate 1 is fed with the vertical sync signal 2 and an integrated version 3 via R1 and C1, the latter giving the average signal level. This automatically corrects the sync polarity to negative active 4, as required by the V.Osc module used (AN5440). In addition, the sync signal is connected via a diode D1 to the free run control circuit node via a resistor R2.