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Digitized Box-In-A-Box Alignment Verniers for Measuring Accuracy of Lithographic Overlays in Integrated Circuit Modules

IP.com Disclosure Number: IPCOM000058185D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Silverman, JP [+details]

Abstract

A technique is described whereby the accuracy and the speed in measuring level to level overlays, as used during the fabrication of integrated circuits, is improved through the use of digitized box-in- a-box alignment verniers. The concept combines two existing techniques so as to obtain increased measurement accuracy and speed. One of the existing techniques uses standard verniers, which consist of two series of parallel lines, one series for each level, with slightly different line spacing (pitch), such that when the patterns from both levels are lined up, the pair of lines (one for each level) that are closest in alignment provide a measurement of the alignment error. If the lines do not touch each other, difficulty will be experienced in determining the best alignment.