High-Speed Divide-By-Ten Counter Circuit With Byte Clock Padding
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15
A technique is described whereby a high-speed divide-by-ten counter circuit, with byte clock padding, features self-starting on power-up and self-correcting and synchronous reset through the use of intermediate stages of combinational logic, as used in fiber-optic link switching networks operating in the gigabit range. A central part of the switching network circuits is the high-speed counter, which must provide byte clock and auxiliary timing and sequencing information. The counter must be self-starting on power-up, self-correcting during operation and capable of synchronous resetting. If the counting sequence is disturbed, the counter must resume proper operation without outside intervention.