Command Dependent Column Address Select Switching
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15
This article describes a scheme to delay column address select (CAS) in a processor during a write operation to allow for data flow through the buffers, but during a read operation CAS is brought earlier. (Image Omitted) One of the problems typically found when increasing performance in a processor system is the slow access time of the memory modules; usually dynamic RAMs (DRAMs). During a read command, the data flow is in the opposite direction than during a write command. Due to this data flow, CAS cannot be activated during a write until much later to allow data to flow through the buffers. In the design disclosed herein CAS is delayed during a write operation to allow for data flow through the buffers, as shown in the timing chart of Fig. 1, but during a read operation CAS is brought earlier.