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Digital Delay Controlled Oscillator

IP.com Disclosure Number: IPCOM000058232D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Ewen, JF Ferrailo, FD [+details]

Abstract

A technique is described whereby a variable frequency oscillator uses a digitally controlled delay stage so as to be compatible with typical digital logic gate arrays. It is digitally controlled for use in phase-locked loop (PLL) circuitry and can operate at high frequencies, in the GHz range. In fiber optic computer data links, a clock recovery circuit is typically required which regenerates timing information from data signals at the receiving end of a data link. The clock recovery circuit must act as a narrowband filter to extract the timing information. One technique used to perform the filtering is a PLL circuit to act as a narrowband filter, whose center frequency is dynamically adjusted to the correct value, through the use of feedback action of the loop itself.