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Method for Patterning Conduction Channels in Field-Effect Devices

IP.com Disclosure Number: IPCOM000058235D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Broers, AN Umbach, CP [+details]

Abstract

A technique is described whereby a method for patterning conduction channels in field-effect semiconductor devices utilizes an electron beam lithographic process so as to produce both negative and positive features in a single exposure of a positive resist. The product is then used to fabricate depletion and accumulation layer field-effect transistors. The concept is an improvement over the conventional lithographic process in that both an insulating structure, which defines the conduction channel and the gate can be fabricated in a single, self-aligned, exposure/lift-off step. In prior art, two exposure/lift-off steps and pattern alignment procedures were required. Various resists are commonly used in the fabrication of semiconductor devices.