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Single-Step, Multilevel, Metalization Technique for Conformal Wiring

IP.com Disclosure Number: IPCOM000058263D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Cronin, JE Kaanta, CW [+details]

Abstract

A technique is described which uses a single chemical vapor deposition (CVD) of metal to achieve a wiring plane with electrical interconnects to levels above and below the wiring plane. VLSI wiring requires planar conductors and insulators. This adds extra process steps and increases process complexity. A simplified process which results in a planarized wiring plane with interlevel interconnect studs is required. Fig. 1 shows one level of insulator with a via defined over first level metal (M1). A second insulator over the first is shown with a trough defined which intersects the defined M1 via. The trough and via are etched using an appropriate etch stop (not shown) between insulators 1 and 2. An alternate is to separately etch the insulators using two masks.