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SELF-ALIGNED P+ IMPLANTED REGIONS FOR COMPOUND SEMICONDUCTOR FETs

IP.com Disclosure Number: IPCOM000058269D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
DeGelormo, JF Jackson, TN Moore, JS Wright, GP [+details]

Abstract

A technique is described whereby field-effect transistor (FET) semiconductors are fabricated with p+ self-aligned regions, so as to reduce short channel effects and parasitic capacitances, without increasing the active gate capacitance. High performance compound semiconductor FETs, such as MESFETs, GaAs gate FETs, MODFETs, etc., have been made using implanted regions self-aligned with a gate structure to reduce the FET source and on resistances. Fig. 1 shows an example of one device, in this case an n-channel self-aligned refractory gate MESFET. As the FET gate length is reduced, for this and similar self-aligned FETs, it becomes increasingly difficult to control the movement of the self-aligning regions under the gate, due to implant straggle and/or diffusion effects.