Browse Prior Art Database

PROCESSOR NATIVE TIMER THIRTY-TWO BIT RIPPLE MAGNITUDE COMPARATOR

IP.com Disclosure Number: IPCOM000058274D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Izquierdo, MR [+details]

Abstract

This article describes a 32-bit ripple comparator using only 63 complementary metal-oxide semiconductor (CMOS) gate array cells. The compare function is performed with less than one-half the number of circuits that a parallel compare implementation requires. The processor native timer comparator is responsible for determining if the contents of the timer register is greater than or equal to the contents of the comparator register. (Refer to Fig. 1 for the block diagram). A parallel implementation can make this determination within one processor microinstruction cycle (120 nanoseconds). However, 133 CMOS gate array cells are needed to realize this implementation. Since the timer register increments at a rate of once every millisecond, it is not necessary to determine greater than or equal to in one cycle.