Browse Prior Art Database

Hardware Accelerator for Processor Level Switching

IP.com Disclosure Number: IPCOM000058278D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Concha, F [+details]

Abstract

This article describes the utilization of hardware to select to which level a processor is to switch, thereby accelerating the level switching function by replacing microcode with the use of hardware. Conventionally, a processor used microcode and the arithmetic logic unit to accomplish the calculation of the next level the processor should go to when executing either a set level status block (SELB) or a level exit (LEX) instruction. The arrangement disclosed herein eliminates the use of multiple microcycles with the use of an 8-bit status register (ST) and two next source fields of the microcode word. The hardware calculates the next level, wait state and the in-process (IP) bit, bit 9 of the level status register (LSR). The drawing is a block diagram of the hardware of this disclosure.