Browse Prior Art Database

HARDWARE ASSIST for a MULTIPOLYNOMIAL BASED CYCLIC REDUNDANCY CHECK for a MULTICHANNEL ENVIRONMENT

IP.com Disclosure Number: IPCOM000058284D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Davis, GT Mandalia, BD Millas, RJ Ortega, OE [+details]

Abstract

This article describes a technique for implementing cyclic redundancy checks for handling multiple channels by sharing a single hardware circuit under microcode control. (Image Omitted) Cyclic redundancy check (CRC) mechanisms have become an integral part of data communication systems and other error correcting systems for storage controllers. Various mathematical techniques are used. In the present integrated services digital network (ISDN)-type application, multiple channels of data streams for communication, as well as multiple polynomials, need to be supported by the same hardware for running on the different channels. (Image Omitted) A digital signal processor is used as an intelligent I/O control processor device to handle full duplex data streams on multiple channels.