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Multi-Processor Communications Interface Disclosure Number: IPCOM000058285D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

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Cash, RC Honomichl, LL Paulsen, PH Rehage, TA Vogelsberg, RE [+details]


This article describes logic circuit interface design and microcode protocol within the microprocessors to implement a processor communications interface. Interfaces between two microprocessors typically require one processor to be the controller and the other to be controlled. Communications between the devices are required to follow predetermined sequences so as to avoid conflicts between the processors. The processors are treated as equals with either processor able to initiate transfers. More than one communication operation may be in progress at any time. The interface design consists of a shared memory area and a set of registers that are exercised through the microcode protocol. The interface is treated as a range of memory addresses and one or more external interrupts by each processor.