Browse Prior Art Database

MINIMIZING INTERNAL RESISTANCE OF GaAs SEMICONDUCTOR DEVICES

IP.com Disclosure Number: IPCOM000058286D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Jackson, TN Rutz, RF [+details]

Abstract

A technique is described whereby the internal resistance between ohmic contacts and the active N-type regions of semiconductor devices, such as those made of gallium arsenide and varying alloys, is minimized by means of ion implantation and diffusion. In the fabrication of GaAs, GaAlAs, GaInAs and similar III-V semiconductor devices, maintaining low intrinsic internal resistance between the ohmic contacts and the active N-type regions of these devices has been a continuing problem. This is especially true in MESFET type of GaAs devices. The concept described herein provides a fabrication method whereby the internal resistance is minimized through the use of ion implantation and diffusion between the source/gate regions and gate/drain regions of the device.