Browse Prior Art Database

Realtime Hardware Redirection of Disk Data Into Multiple Noncontiguous Cache Memory Pages

IP.com Disclosure Number: IPCOM000058289D
Original Publication Date: 1988-Sep-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Boudreaux, RP Oliver, JK [+details]

Abstract

This article describes a technique in a processing system which eliminates sector interleave on hard disk devices due to microcode intervention between sector transfers to noncontiguous addresses in cache memory. On typical high performance disk systems, a cache memory is used to reduce read access time for frequently read data areas on hard disks. The cache memory is organized in pages (usually 2K bytes of data) and dynamically allocated as new data areas are accessed. This results in a cache data block cross-reference table in which logically sequential data pages are in physically disjointed locations in memory. As a result, when memory pages become free for new data, the new data is transferred into memory in separate operations.