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Multiple Grid Permeable Transistor

IP.com Disclosure Number: IPCOM000058305D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Delage, SL Iyer, SS Sai-Halasz, GA [+details]

Abstract

A technique is described whereby multiple independently biasable grids are imbedded in a single crystal semiconductor matrix, so as to provide a high output impedance solid state device. The grids are designed to improve the performance of permeable base transistors (PBTs) which display low output resistance characteristics. (Image Omitted) Typically, PBT high speed devices have a metallic grid embedded in a semiconductor matrix, as shown in Fig. 1a. In this structure, the potential inside the grid spacing is controlled by the Schottky junction properties of the grid and by whatever bias is applied between the grid and the other side of the semiconductor. Generally, one side of the grid is referred to as the emitter and the other side as the collector, while the grid contact is considered the base.