Browse Prior Art Database

Improved Centrality Wafer Fabrication

IP.com Disclosure Number: IPCOM000058318D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Snyder, GL Walker, JJ [+details]

Abstract

A common centrality pattern design has been proposed for use on all masterslices of semiconductor wafers used for calibrating E-beam and optical exposure tools. It would replace a cumbersome approach to fabricating initialization, or centralization, wafers. The centrality wafers are wafer standards which are exposed on an E-beam tool and then used to calibrate mask centrality of optical exposure tools. The calibration is necessary because of the E-beam lithography tool's limited tolerance for wafer rotation. Each masterslice previously required a new E-beam deflection and two unique pattern designs. In previous methods, a pattern was designed for each masterslice and extended out to the chip boundary limits A (Fig. 1).