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LATCH-TO-LATCH DELAY TESTING in LSSD USING a THREE-LATCH SRL

IP.com Disclosure Number: IPCOM000058323D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
McAnney, WH Savir, J [+details]

Abstract

Latch-to-latch delay testing of a path in combinational logic requires applying two successive vectors. Both vectors must sensitize the required path, and the second vector must cause a transition to propagate along the path to a capturing latch. The test is successful if the propagation time of the second vector from launching latch to capturing latch is less than the allowable delay. (Image Omitted) In LSSD, test vectors are shifted into SRLs along a scan path. In a standard two-latch SRL, many logic input changes occur while a test vector is being scanned. These changes prohibit the application of the two successive vectors needed for a delay test. To avoid this problem a special three-latch SRL which can load two independent data bits is needed. The three-latch SRL (Shift Register Latch) is shown in Fig. 1.