Parallel Port Shift Register Latch for Built-In Delay Testing Using Data Compression
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15
This invention relates to delay testing of combinational logic in double-latch LSSD structures and, more particularly, to a means for performing the delay test without any scan operations. This invention shows the simultaneous loading of independent test vectors into parallel ports in each shift register latch (SRL) of a LSSD structure to shorten test sequence time and permit a delay test. During a test of a standard LSSD structure, a scan-in/scan-out operation using non-overlapping shift clocks is used to serially load a test vector to the successive SRLs and simultaneously to unload a test response vector. This mode of operation has two problems: the time consumed by scan operations is much greater than the actual test time, and the shifting operation means that delay tests are restricted to a limited set of test vectors.