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Distributed Generation of Non-Uniform Random Patterns for Circuit Testing

IP.com Disclosure Number: IPCOM000058331D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
McAnney, WH Savir, J [+details]

Abstract

Two LSSD shift register latch (SRL) designs are described for the generation and application of either low, uniform, or high density random patterns for a test sequence. In Fig. 1, the first design, L1 and L2 are LSSD latches and together they form an SRL. When clocks T, L5, and L6 are held off, the SRL functions as a system latch using data input D with clock C or as a shift register element using data input I with clocks A and B. See U.S. Patents 4,503,537 and 4,513,418 for more information. (Image Omitted) L5 and L6 are latches similar to L2. L2 data is gated into L5 using clock L5 or into L6 with the L6 clock.