Browse Prior Art Database

Processor ROS Simulator

IP.com Disclosure Number: IPCOM000058353D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
DeLahoz, L Izquierdo, MR Kantner, RF [+details]

Abstract

This article describes a technique for simulating the microcode read- only storage (ROS) for a processor. It provides the capability of downloading the microcode from a host processor where the object code resides and allows debugging the microcode in conjunction with the processor hardware. (Image Omitted) The processor ROS simulator system disclosed herein is configured as shown in Fig. 1. Fig. 2 is a block diagram of the ROS simulator. It has a communications port that attaches to a personal computer (PC) for its user interface. The simulator plugs directly on the backboard of the host processor. Microcode can be downloaded from the processor where the assembled code resides. Microcode patching is available which allows the microcoder to observe if this patch fixed the problem before committing to a new revision level.