HIGH PERFORMANCE GaAs FET DEVICE STRUCTURE
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15
A process is described for fabricating high-performance GaAs field- effect transistor (FET) devices having submicron channel length, low source resistance, and low subthreshold leakage. The device structure includes dielectric sidewall spacers between the ohmic contacts to source/drain regions and gate metal, and P+ regions just below edges of the channels. (Image Omitted) Fabrication would begin with a GaAs substrate 1 at the top of which a buffer layer of GaAs may have been grown. Using a photoresist mask, N- regions 2 are formed through ion implantation of a suitable N dopant. A thick layer of SiOx 3 is formed on the substrate surface followed by a polysilicon layer 4. As illustrated in Fig.