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Analog Cmos Masterslice Technique Disclosure Number: IPCOM000058370D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

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Gruver, MR Morgan, CW Owens, BR Sobotta, PE [+details]


This integrated circuit layout technique provides a method to create a wide range of device sizes for both n channel and p channel FET transistors while still allowing masterslice pre-processing of 50% of the mask levels. The figure shows how basic N channel transistors of different sizes can be built using a technique called "gate isolation". Two predefined RX rectangles are defined for the masterslice. Adjacent devices in the same RX shape are isolated from one another by the use of polysilicon gates which are permanently tied to ground (or VDD for the p channel case). This piece of "gate isolation" is effectively a transistor which is always off. Note that a transistor can be built of virtually any aspect ratio (W/L).