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On-Chip Receiver Circuit Design

IP.com Disclosure Number: IPCOM000058383D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Austin, FD Bansal, JP Puri, YK [+details]

Abstract

When a tristate off-chip-driver switches from an active state to a high impedance state and remains in this state for one or more machine cycles, a net driven by the driver will float and may drift to a lower or higher potential. The net may even oscillate due to leakage and/or coupled noise from other nets and introduce logical errors in the operating system. Figs. 1 and 2 show a receiver circuit which overcomes this problem without deteriorating the performance or increasing power dissipation. In Fig. 1, T1 and T2 serve as pull-up and pull-down devices, respectively, for an input level appearing at terminal 10. When the input is "up," a node 1 is "down," a node 2 is "up", and a node 3 is "down" and an output appearing at terminal 12 is "up.