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Offset Control for a Bus Driver Circuit

IP.com Disclosure Number: IPCOM000058386D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Ceccherelli, JC [+details]

Abstract

A bus driver circuit is disclosed which maintains the low level output voltage of a logic device regardless of the current flow or the device temperature. In an existing bus driver circuit of Fig. 1, the output offset is determined by the saturation voltage of Q1 and the forward voltage drop of D1. The output is an open collector and in application is terminated to 2 volts via two 30-ohm resistors at each end of the line. When one output is active, it must sink approximately 70 milliamps to pull the bus at the output to the desired 1-volt low logic level. With one output active and sinking 70 milliamps, the output low level should range between 1.15 volts and .88 volts over a temperature range. Since this driver is used in wired OR application, up to 32 outputs can be active on the same line at the same time.