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Method of Partitioning a CMOS ROM Array to Enhance Performance

IP.com Disclosure Number: IPCOM000058403D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Hovis, WP Kauffmann, BA [+details]

Abstract

The performance of a CMOS ROM array can be enhanced by partitioning the array using column line pass devices and bit line restore devices, thereby reducing the capacitive load of the bit lines by factors of 1/2, 1/4, 1/8, etc., depending on design goals. In dense ROM array designs, partitioning is utilized to reduce signal development time which is a function of array device size and capacitance the device must discharge. Traditional methods of partitioning an array in the bit direction to halve the capacitive load require the placement a bit decoder in the center of an array and double ending its operation as shown in Fig. 1a. Further partitioning would require doubling the number of bit decoders and pass devices, etc.