Browse Prior Art Database

Eight by Sixty-Four to One CMOS Switch Matrix Macro

IP.com Disclosure Number: IPCOM000058407D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Carrig, KM Jasmin, JE Klein, GW Selleck, JE [+details]

Abstract

This is a CMOS switch matrix macro with staggered gating of off-chip drivers (OCDs) for products that require unidirectional or bidirectional switching matrices with or without redundancy. Three levels of multiplexing are usually required to achieve a switching capability of 64 x 1, and each stage requires separate decoding. Because the 8 x 64 x 1 switch matrix macro reduces the number of decoding circuits and total switching delay, the macro can be implemented where simultaneous switching of OCDs normally results in switching problems. It can also be used where redundancy and/or bidirectionality is required. The six address bits required to select 1 out of 64 are divided into two groups, i.e., three high-order bits and three low-order bits.