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High Density Gate Array Cell

IP.com Disclosure Number: IPCOM000058411D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Kemerer, DW Kilmeyer, RD [+details]

Abstract

By requiring only one vertical metal wire for each pair of gates and output diffusions, an increased layout density is achieved. Adjacent circuits are electrically isolated from each other by connection of the gate of one unused transistor to the high voltage supply VDD and the gate of a second unused transistor to ground potential. Fig. 1 is a schematic of a complementary metal oxide silicon (CMOS) 2-way NAND gate. Fig. 2 is a layout of that NAND gate and the isolation between circuits. An n-type diffusion n interconnects the source of transistor T2 to the drain of transistor T1. Gates of transistors T1 and p-type transistor T3 are connected by vertical metal line A. Gates of transistors T2 and p-type transistor T4 are connected by vertical metal line B. Drains of transistors T3 and T4 are connected by p-type diffusion p.