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Chip Enable Access Speed Up Circuit for Asynchronous SRAM

IP.com Disclosure Number: IPCOM000058417D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Lee, HS [+details]

Abstract

A circuit is shown for masking out the restore period at the beginning of a chip enable (CE) access cycle during synchronous operation of a static random-access memory (SRAM) by generating a masking pulse. When CE goes negative, a chip is selected and memory lines, word or bit, become activated by their respective timing circuit outputs. However, due to the use of power standby techniques for saving power at the chip enable not (CEN) gated NAND/NOR address buffers, the CEN signal input often (address dependent) triggers an address transition detector (ATD) circuit. This results in a false single-shot timing pulse immediately following the CEN input signal and causes a redundant precharge period to begin.