Browse Prior Art Database

Reliable and Extendable Wiring Process for Logic

IP.com Disclosure Number: IPCOM000058426D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Cote, WJ Cronin, JE Holland, KL Kaanta, CW [+details]

Abstract

A semiconductor metallization fabrication process is disclosed which utilizes dielectric planarization prior to wiring personalization steps to interconnecting multiple levels of metal. Through a single blanket deposition, both a metal line and a stud having edges that are self- limited by the metal line are formed. (Image Omitted) In order to simplify the process steps used to interconnect multiple layers of wiring, planarization at every level is essential for imaging each layer as well as eliminating and minimizing the processing steps used for fabricating the interconnecting conductors. The process proceeds as follows: 1. An initial planarization step is carried out on the boron phosphosilicate glass (BPSG) that is coated on the transistors (Fig. 1).