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FAST CARRY COMPUTATION WITH CASCODE CIRCUITS

IP.com Disclosure Number: IPCOM000058436D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

This circuitry and connection scheme for fast carry for adder circuits in semiconductor devices allows a 32 bit carry to be computed in 3 stages of 4-level cascode circuits. Adder carry computation is a main delay in arithmetic units. Various methods have been proposed to reduce the propagation delay time [1,2,3] with carry lookahead [2] being used most. The fast carry computation scheme proposed uses cascode circuits. (Image Omitted) Conditional carries are realized along the cascode tree up to the cascode levels in the technology. In this manner multiple ripple operations are performed serially, but in one circuit stage delay, with no need of excessive FANINs or FANOUTs. Propagation is further accelerated towards the more significant direction by cascoding the conditional carries.