Bus Locking Scheme for an Interleaved-Bus Multi-Processor System
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15
This article describes a new bus-locking scheme for a multiprocessor system with a two-way interleaved bus connection. The new bus-locking scheme consists of a bus arbitration logic and a control logic to effectively lock both even and odd buses. In Figs. 1 and 2, illustrating state transitions of the logic, the following signals are used to specify transition conditions of the logic. 1.iLOCK: specifies that the MPU requests the bus to be locked. 2.aCR: is activated by the arbitration logic whenever an access right of the bus is obtained. 3. BUSYC: is activated by the control logic of the counterpart bus (odd bus for the even bus, and even bus for the odd bus) to indicate that it has already got the access right. (Image Omitted) 4.