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Low Power Dissipation Vertical Deflection Circuit Using a Commercial Monolithic Integrated Circuit

IP.com Disclosure Number: IPCOM000058450D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Kobayashi, M. [+details]

Abstract

This article describes a lower power dissipation vertical deflection circuit. The disclosed technique uses a commercial monolithic IC of vertical deflection which has signal process and output function with a double voltage of +B retrace pulse generator and is provided with a voltage rail switch circuit during retrace time together with the IC instead of a capacitor for double voltage generation. The newly developed circuit can realize the narrow blanking time without increasing the power dissipation coming from low impedance yoke. The added switching circuit instead of double voltage generation capacitor supplies a higher voltage to make the retrace time shorter. The figure shows a circuit diagram with the equivalent circuit of a part of an internal IC and peripheral components for vertical deflection.