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Microcode-Controlled Channel Interface

IP.com Disclosure Number: IPCOM000058468D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Gould, JM [+details]

Abstract

A channel interface that incorporates a microcode-controlled engine provides a versatile, easily adaptable link between a host computer channel and any one of a variety of microprocessors. (Image Omitted) An example of a microcode-controlled channel interface is shown in Fig. 1 and consists of three subsystems, a microcoded engine 1, data interface 2, and processor or microprocessor interface 3. Engine 1 is specially microcoded to handle all sequencing and is diagrammed in Fig. 2. Its inputs include sixteen-bit multiplexer 4, 32-bit multiplexer 5, and sixteen-bit compare circuit 6. These are connected to counter 7, random-access memory (RAM) 8 and decoder 9 with 64 outputs. The inputs are single bit signals from either the channel (TAGS OUT) or the connected microprocessor.