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Exception Retry in a Parallel Vector Processor Disclosure Number: IPCOM000058485D
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-15

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Ngai, CH Watkins, GJ [+details]


A parallel vector processor is implemented via a configuration of individual element processors, and the resulting design has a parallel implementation for the purpose of achieving a high performance operation. However, the System/370 vector architecture, to which the design must conform, is essentially a serial architecture approach. For example, if a vector ADD of two 128 element registers was being performed, and an overflow exception occurred in the ADD operation on element #10, the architecture specifies that the results of elements 11 to 128 must remain unchanged. This is easily detected in a serial pipeline-type machine, because when element #10 is being processed, and the exception is detected, the operation can be terminated and easily restarted on element #10.