Distributed Clock Control and Synchronization
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-15
This invention provides a means of distributing a clock control function across all of the chips in a design. Timing hazards related to critical delay requirements on clock gating signals are eliminated, while the number of chip I/O pins needed is greatly reduced. Yet, the capabilities of a centrally located clock control scheme are preserved; all the system clocks can be stopped or started in synchronization for IPL or the service and debug functions. (Image Omitted) On past IMPI (international machine program interface) processor designs, clocks were generated and controlled within one isolated area of logic (specifically, on one chip). With the subject processor, each major chip generates its own system clocks, and control of these clocks becomes more difficult. Fig.