Placement-Preserving Timing Adjustment for Very Large-Scale Integrated Circuits
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-15
A technique is described whereby circuitry, as used in very large-scale integrated (VLSI) circuits, can be modified when timing problems become apparent after circuit placement and wiring. Discussed is a timing adjustment procedure utilizing placement- derived net capacitance estimates in computing path delays. The described method does not perturb the original placement and therefore leads to a convergent process for correcting timing violations. Typically, timing constraints are initially addressed during the logical phase of VLSI chip design. Logic synthesis programs produce a design which meets timing requirements under the assumption that the circuits have known delays and that all connections have a single, average length.