Browse Prior Art Database

Floating-Point Unit Parallel Structure

IP.com Disclosure Number: IPCOM000058515D
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Goldberg, WD Olsson, B Rodriguez, JR Suarez, GA [+details]

Abstract

This article describes in a floating-point processor the structural aspects of a parallel logic as well as aspects relevant to the routing of overlapped operations through that structure. Two aspects of the parallel nature of the design are the pipelined organization and the parallel execution by means of multiple independent functional units. High-performance arithmetic processors use techniques of instruction execution overlap, such as pipelining, in order to optimize the performance level of the processor. These techniques apply freely in high-end processors, where the technologies used offer significant freedom of design, but they are not easy to apply to a low-end proces (Image Omitted) sor design where the limitations of the technology are significant.