Fast Reset of Logical Facilities
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-15
This article describes an improvement to the operation of a large, multiple-pipeline processor with parallel instruction execution. In order to realize the full potential of these attributes, past machines have incorporated a method for maintaining multiple copies of certain machine facilities, such as registers, thus minimizing the effect of the inherent interlocks between instructions. Methods have also been employed, using some of this same hardware, for canceling the effect of instructions that have been decoded but not fully completed, thus providing a retry capability. Table 1 contains the mapping of Logical or Programmable Facilities 2 to Physical Facilities 3 entries as viewed by instruction decode. Table 4 contains the status of each entry in Facilities 3 as pertaining to its usage by the pipeline.