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Performance Improvement by Use of All-Inclusive Dynamic Look-Aside Table Hardware

IP.com Disclosure Number: IPCOM000058597D
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-15

Publishing Venue

IBM

Related People

Authors:
Boguski, MJ Callahan, RW Kodukula, S Thorne, RE [+details]

Abstract

IBM System/370 processors utilize a dynamic look-aside table (DLAT) mechanism through which virtual addresses are translated to real addresses. Conventional DLAT mechanisms utilize an array of such size that translation information regarding only one subset of the virtual memory is available at any one time. If the processor is to access memory for which no information is currently available, an exception condition is generated. The resolution of this exception condition incurs a tangible performance degradation. An all-inclusive DLAT, shown in the block diagram, uses an array of sufficient size and design that it may simultaneously hold translation information regarding all pages of the 16 Meg virtual memory.