Accurate, Low Power, Self-Clocked CMOS Decoder
Original Publication Date: 1988-Nov-01
Included in the Prior Art Database: 2005-Feb-15
This disclosure describes a clocked decoder designed for CMOS technology. The main characteristics of that circuit are its very low transient power dissipation, and its very high tolerance to process variations and environment changes (temperature, power supply, etc.). These goals have been achieved by means of the inherently low power clocked NAND decoder and also by usage of a Set-Reset Word Decoder (SRWD) clock generator. The SRWD signal controls the decoder delay operation with the help of a signal which propagates in that SRWD clock through the image (dummy) electrical path existing in the decoder. (Image Omitted) The SRWD clock generator and the 1/128 decoder in which the two signals - RWD (Reset Word Decoder) and SWD (Set Word Decoder) - are applied are shown in Fig. 1.